There is a continued push by manufacturers of electronics to increase functionality of electronic devices. Greater functionality in an electronic device can provide additional processing power within the same package or increased convenience by reducing the total number of electronic devices. For example, rather than carrying a cellular telephone, a pager, and a personal digital assistant (PDA), a user can carry a single electronic device that has the combined functionality of the cellular telephone, the pager, and the PDA.
Increasing the functionality of an electronic device can require the integration of additional electronics into the electronic device. Without a concurrent change in process technology that can help reduce power consumption, an integrated circuit with an increased number of devices will tend to consume more power than an integrated circuit with fewer devices. Therefore, given a fixed battery capacity, a battery powered electronic device with increased functionality will require more frequent charging of the battery or a battery with greater capacity.
A technique that can help to reduce the power consumption of an integrated circuit is to design the integrated circuit with multiple power domains, with each power domain containing a subset of the overall functionality provided by the integrated circuit. For example, a first power domain can contain two unique functions, a second power domain can contain a single unique function, and so forth. Then, when the functions of the integrated circuit within a power domain are not being used, the power being provided to the circuitry within the power domain can be eliminated. Since no power is provided to the circuitry, the circuitry consumes no power. Alternatively, the circuitry within a power domain that performs the functions can be placed into a sleep or hibernate mode. When in the sleep mode, the circuitry can consume a very small amount of power. It may be possible to reduce power consumption in sleeping circuitry to substantially zero.
A diagram shown in FIG. 1a illustrates an integrated circuit 100. The integrated circuit 100 contains circuitry that has been partitioned into multiple multi-voltage threshold design blocks, such as multi-voltage threshold design blocks 105 and 106. The multi-voltage threshold design blocks 105 and 106 are independently coupled to power rails Vdd and Vss. The coupling of the multi-voltage threshold design blocks 105 and 106 to the power rails Vdd and Vss can enable the decoupling of one or both of the design blocks 105 and 106 from the power rails without affecting the power delivery to other design blocks in the integrated circuit 100.
To decouple a multi-voltage threshold design block from the power rails, it is necessary to sever the current path through the multi-voltage threshold design block. Diagrams shown in FIGS. 1b and 1c illustrate two prior art techniques for severing the current path through the multi-voltage threshold design block 105. Both prior art techniques use a switch that is serially connected between the multi-voltage threshold design block 105 and one of the two power rails. When the switch is open, the current path between the multi-voltage threshold design block 105 and the two power rails is interrupted and power to the multi-voltage threshold design block 105 is cut-off. When the switch is closed, the current path between the multi-voltage threshold design block 105 and the two power rails is established, permitting current flow through the multi-voltage threshold design block 105.
The diagram shown in FIG. 1b illustrates the use of a switch 110 serially connected between the Vdd power rail and the multi-voltage threshold design block 105. Since the switch 110 is at the head of the multi-voltage threshold design block 105, it is commonly referred to as being a header switch. An electrical node between the header switch 110 and the multi-voltage threshold design block 105 can be referred to as a virtual Vdd or VVdd. The diagram shown is FIG. 1c illustrates the use of a switch 115 serially connected between the multi-voltage threshold design block 105 and the Vss power rail. Since the switch 115 is at the foot of the multi-voltage threshold design block 105, it is commonly referred to as being a footer switch. An electrical node between the header switch 110 and the design block 105 can be referred to as a virtual Vss or VVss.
Since the header switch 110 and the footer switch 115 are typically implemented as one or more MOS transistors, there is a voltage drop across the header switch 110 and the footer switch 115. Therefore, the voltage at VVdd or VVss is not exactly equal to the voltage at the Vdd power rail or the Vss power rail.
One disadvantage of the prior art technique of using a switch (either a header switch or a footer switch) to control the current path through a multi-voltage threshold design block is the sizing of the switch. If the switch is large, to meet performance requirements, for example, then turning on the switch can cause a significant glitch. On the other hand, if the switch is small, to meet electron migration requirements, for example, then the switch may not be able to provide adequate current to the multi-voltage threshold design block within timing requirements.